For firms competing in modern high-frequency trading (HFT), latency optimization is no longer about one breakthrough. It's about removing tens of nanoseconds across hundreds of components while maintaining deterministic behavior. The fastest participants combine exchange colocation, custom hardware, optimized network design, and software tuned specifically for predictable execution rather than average performance.
Here's what a state-of-the-art stack looks like.
1. Physical colocation
The biggest latency reduction is still geographic.
Typical setup:
- Rent cabinets inside the exchange's primary colocation facility.
- Use the shortest available cross-connects.
- Place market data handlers, order gateways, and FPGA appliances in the same rack when possible.
- Eliminate unnecessary cable length (even a few meters matter).
Large firms often have infrastructure colocated at multiple exchanges simultaneously:
- Equities
- Futures
- Options
- Crypto venues
with dedicated infrastructure at each.
2. Layer 1 network design
Modern HFT networks increasingly avoid traditional enterprise networking.
Typical topology:
Exchange
│
Cross-connect
│
FPGA NIC / Feed Handler
│
Low-latency switch
│
Trading servers
Goals:
- zero oversubscription
- no spanning tree
- no unnecessary routing
- one-hop paths wherever possible
Many firms even avoid switches entirely for critical paths if direct links are feasible.
3. Low-latency switches
Commodity switches are generally too slow.
Popular choices include:
- Arista 7130 series (formerly Metamako)
- Cisco Nexus ultra-low latency models
- Juniper low-latency products
Characteristics:
- 3–10 ns forwarding
- deterministic latency
- FPGA programmability
- hardware timestamping
Modern FPGA-based switches can also perform:
- packet filtering
- multicast replication
- feed arbitration
- timestamp insertion
without CPU involvement.
4. FPGA everywhere
One of the biggest trends over the past decade has been moving logic into hardware.
Common FPGA functions:
Market data
- UDP parsing
- multicast handling
- order book construction
- feed normalization
Trading
- signal generation
- risk checks
- quote generation
Networking
- packet modification
- timestamping
- protocol translation
Some firms place their first trading decision directly inside the FPGA.
Software receives only higher-level events.
5. Kernel bypass
The Linux networking stack is far too expensive for ultra-low latency.
Common technologies:
- Solarflare/OpenOnload
- DPDK
- RDMA
- XDP/eBPF (for some workloads)
- vendor-specific user-space drivers
Goal:
NIC
↓
Userspace
instead of
NIC
↓
Kernel
↓
Userspace
Kernel bypass typically removes several microseconds of latency while reducing jitter.
6. FPGA NICs and SmartNICs
Standard NICs are increasingly replaced by programmable devices.
Examples include offerings from major FPGA and SmartNIC vendors.
Capabilities:
- hardware order book building
- packet filtering
- timestamping
- order generation
- deterministic packet scheduling
Many execute protocol parsing entirely in hardware.
7. CPU optimization
The fastest CPUs aren't necessarily the highest-core-count models.
Typical priorities:
- highest single-thread frequency
- large L3 cache
- predictable turbo behavior
- NUMA awareness
Configuration often includes:
- isolated cores
- disabled SMT/Hyper-Threading (for latency-critical threads)
- huge pages
- CPU pinning
- real-time scheduling
- fixed CPU frequency
- minimized BIOS power management
8. Memory optimization
Latency-sensitive systems try to avoid:
- page faults
- cache misses
- NUMA penalties
- dynamic allocation
Techniques include:
- lock-free queues
- preallocated memory pools
- huge pages
- cache-line alignment
- careful data layout
- avoiding false sharing
9. Operating system tuning
Typical Linux tuning includes:
- isolated CPUs
- nohz_full
- RCU offloading
- IRQ affinity
- disabling power-saving C-states
- disabling frequency scaling
- disabling unnecessary daemons
- disabling swap
- minimal kernel configuration
Many firms also use real-time or heavily customized Linux kernels.
10. Time synchronization
Accurate timestamps are essential for both performance analysis and regulatory compliance.
Current best practice includes:
- PTP (IEEE 1588)
- hardware timestamping
- GNSS receivers
- atomic clocks or disciplined oscillators for holdover
Synchronization accuracy is typically in the sub-microsecond range, and often much tighter within a colocated environment.
11. Microwave and millimeter-wave links
For inter-city trading, fiber isn't always the fastest option.
Examples:
Chicago ↔ New Jersey
Traditional fiber:
~13–14 ms one way
Microwave:
~8–9 ms
Millimeter-wave:
Similar, depending on conditions
Free-space optical:
Used selectively where practical
Microwave remains attractive because electromagnetic waves travel closer to the speed of light in air than in fiber, which has a lower propagation speed due to its refractive index.
12. Software architecture
State-of-the-art software minimizes work in the critical path.
Typical pipeline:
Packet arrives
↓
Hardware timestamp
↓
FPGA parsing
↓
Userspace feed handler
↓
Strategy
↓
Risk check
↓
Order generation
↓
NIC
↓
Exchange
Characteristics:
- single-threaded hot path
- lock-free communication
- no logging on the critical path
- no system calls
- no memory allocation
- branch prediction optimization
- vectorized parsing where useful
13. Latency measurement
Top firms continuously profile latency at nanosecond resolution.
They measure:
- wire-to-wire latency
- market-data-to-decision latency
- order-to-wire latency
- jitter distributions (not just averages)
- tail latency (e.g., 99.9th and 99.99th percentiles)
Hardware timestamps from NICs and switches are preferred over software timing.
14. Emerging trends
Recent areas of focus include:
- FPGA-first architectures: More preprocessing and even strategy logic in programmable hardware.
- Hardware-accelerated networking: SmartNICs and programmable switches handling increasingly complex packet processing.
- AI for research, not execution: Machine learning is widely used offline for signal discovery and model development, but latency-critical execution paths generally rely on deterministic algorithms because inference latency and variability are difficult to justify at the fastest timescales.
- Optical interconnects: Growing interest in co-packaged optics and silicon photonics to reduce bandwidth bottlenecks and power consumption within data centers.
- Deterministic systems: Engineering effort is often directed at reducing latency variance ("jitter") as much as reducing median latency.
Example of a modern ultra-low-latency rack
Exchange
│
Cross-connect
│
FPGA Switch
│
FPGA Feed Handler
│
Trading Server
• Kernel bypass
• Isolated CPU cores
• Huge pages
• Lock-free engine
│
FPGA NIC
│
Exchange
Where the frontier is today
Among the most advanced HFT firms, optimization has shifted from eliminating whole milliseconds or even microseconds to shaving tens of nanoseconds from packet handling, cache access, serialization, and switching. The competitive edge comes from treating the entire system—from fiber length and switch architecture to FPGA logic, CPU cache layout, and software design—as a single end-to-end latency budget. Success is measured not only by the lowest median latency but also by maintaining extremely tight latency distributions under sustained market load.
